I'm getting into understanding jfets. Found runoffgrooves jfet schematic that tests for Idss and Vp. Now there are two designs up on tagboard. One has a 47 uF cap, the other has that cap and an ic. These differ from the one I found from rog. Yet I can't find any info on why these components were added. So I was just wanting to figure out how to translate this schem to vero, the one from rog's article. http://www.runoffgroove.com/fetzervalve.html
Schematic for tester is at the bottom.
I've drawn it on paper but I don't know if it is correct.
This gives some background, and includes a version with the cap and op amp. http://geofex.com/Article_Folders/fetmatch/fetmatch.htm
That one is for measuring just vgss off. The ones I'm inquiring about are for measuring both Idss and vp.
This one will do both. The schematic omits the -9V supply that's present on the vero, but that's just the TC1044 IC1, plus C1 and C2, feeding -9V to pin 4 of IC2. You can use a second 9V battery for the -9V supply and simplify it. Note that R1 (100 ohm) is 0.1% tolerance, not the usual 1%.
Quote from: mauman on September 18, 2021, 02:22:43 PM
This one will do both. The schematic omits the -9V supply that's present on the vero, but that's just the TC1044 IC1, plus C1 and C2, feeding -9V to pin 4 of IC2. You can use a second 9V battery for the -9V supply and simplify it. Note that R1 (100 ohm) is 0.1% tolerance, not the usual 1%.
So this vero is correct? I can build as shown and it'll work?
Yep, it's verified.
Thanks!
great thanks